The present invention relates to the manufacture of integrated circuits on a substrate. More particularly, the invention relates to a method and apparatus for reducing plasma charge damage when such integrated circuits are manufactured using a plasma processing technique.
One of the steps in the fabrication of modern semiconductor devices is the formation of a thin film on a semiconductor substrate by chemical reaction of gases. Such a deposition process is referred to as chemical vapor deposition (“CVD”). Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. Plasma-enhanced CVD techniques, on the other hand, promote excitation and/or dissociation of the reactant gases by the application of radio-frequency (“RF”) energy to a reaction zone near the substrate surface, thereby creating a plasma. The high reactivity of the species in the plasma reduces the energy required for a chemical reaction to take place, and thus lowers the temperature required for such CVD processes as compared to conventional thermal CVD processes. These advantages are further exploited by high-density-plasma (“HDP”) CVD techniques, in which a dense plasma is formed at low vacuum pressures so that the plasma species are even more reactive.
Any of these CVD techniques may be used to deposit conductive or insulative films during the fabrication of integrated circuits. A common configuration requires deposition of oxide material over a series of metal lines such as shown in FIG. 1(a). In this configuration, metal lines 206 extend in the direction perpendicular to the figure. Each metal line 206 is electrically connected to a gate 208 at a lower level, which is separated from the substrate 202 by a gate oxide 204.
In order to illustrate the charging effects that take place when depositing a film on such a structure, two extreme conditions are considered. The first is illustrated in FIG. 1(b), which shows a highly nonconformal deposition of film 210 over the series of metal lines 206. Such a growth pattern may be termed “neutral-flux-limited oxide growth” and results when the thickness of film 210 increases proportionally to the flux of neutral precursors arriving at a surface segment of the metal-line pattern. The deposited layer 210 is thicker on top of the metal lines 206 than at the bottom of the gaps between them or at the sidewalls. This is a consequence of geometric shadowing of the isotropic neutral precursors by the topography. The second extreme condition is illustrated in FIG. 1(c), which shows conformal deposition of film 210 over the series of metal lines 206. This growth pattern may be described as “reaction-rate-limited oxide growth” and results when the film thickness is independent of the neutral precursor flux. Under such highly idealized conditions, the film surface is the same on all surfaces at all times. Realistic deposition processes behave in a manner intermediate between the extremes illustrated by FIGS. 1(b) and 1(c).
During deposition of oxide material, the metal lines 206 acquire a charge even if initially neutral. Such charging results from a combination of tunneling currents that are generated through the oxide layer at the top and sidewalls, surface currents that are generated along the sidewall and bottom surface, and electron tunneling through the gate oxide from the substrate. FIGS. 1(d) and 1(e) illustrate the currents that are generated during deposition of the oxide layer for neutral-flux-limited growth and reaction-rate-limited growth respectively. The directionality difference between ions and electrons as they cross the forming layer results in a differential charging pattern so that in addition to acquiring a charge, the metal line is subjected to potential gradients.
In particular, electron shading leads to the accumulation of negative charge at the upper sidewalls of the forming layer, while directional ions positively charge the forming surface in the gaps. The combination of a negative potential at the upper sidewall with a positive potential at the gap bottom preferentially deflects less energetic ions towards the sidewall, causing the lower part of the sidewall also to acquire a positive charge. Surface currents ensure that no surface potential gradients larger than a threshold value exist, but large electric fields are generated in the oxide layer, particularly near the top and bottom of the sidewalls where surface potentials approach extreme values.
The oxide field also depends on the metal line potential and the thickness of the oxide layer at each point. It is this thickness dependence that causes deposition of a nonconformal oxide to result in greater metal-line charging and increased gate oxide damage, as shown in FIG. 1(d). In both FIGS. 1(d) and 1(e), positive tunneling currents are illustrated with arrows, the thickness of the arrow being roughly proportional to the size of the current. For nonconformal deposition [FIG. 1(d)], a large positive current flows to the metal line 206 through the sidewall bottom region where the oxide is thinnest. During the early stages of oxide growth, this current is compensated mostly by electron tunneling from the upper sidewall region, with the current through the gate oxide being comparatively smaller. As the oxide thickness at the upper sidewalls increases, there is a corresponding decrease in the electron tunneling current there, forcing the current through the gate oxide to increase to compensate for the excess current flow through the sidewall bottom.
Conversely, during conformal deposition [FIG. 1(e)], the thickness of the film increases at the same rate at the top and bottom of the sidewall as the film is deposited, causing a simultaneous decrease in the positive and negative tunneling currents. Since there is no excess current flow through the sidewall bottom, the compensating current through the gate oxide can remain small. The thickness of the layers in both FIGS. 1(d) and 1(e) has been exaggerated for illustrative purposes; charge damage is caused well before the deposited films reach the thicknesses shown.
This description of the mechanism by which destructive currents are produced during plasma-enhanced CVD is somewhat schematic; a more complete analysis is provided in Gyeong S. Hwang and Konstantinos P. Giapis, J. Appl. Phys. 84, 154 (1998), which is herein incorporated by reference for all purposes. Moreover, while the description has focused on the generation of currents during deposition, similarly destructive currents are generated during plasma-enhanced etching processes. As a result, both deposition and etching processes that use plasma processes to form integrated circuit structures can damage microstructure components by, e.g., causing sidewall irregularities (notching, bowing, etc.) and/or latent gate oxide degradation. Such charging damage is known to be greater for etching higher aspect-ratio structures, where the aspect ratio is the ratio of the height of a gap to its width, and is expected also to be greater for deposition processes on structures with higher aspect ratios. Since efforts are continually being made simultaneously to decrease the critical structural dimensions and to increase the aspect-ratio capacity of such processes as part of the ongoing quest to pack logic devices more densely, it is desirable to have a process by which the charging damage can reduced.